SH7727 Datasheet, PDF (462/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bits 13 and 12—Source Address Mode 1, 0 (SM1 and SM0): SM1 and SM0 select whether the
DMA source address is incremented, decremented, or fixed.
Bit 13: SM1
Bit 12: SM0
Description
0
0
Fixed source address*
(Initial value)
1
Source address is incremented (+1 in 8-bit transfer, +2 in 16-
bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer)
1
0
Source address is decremented (–1 in 8-bit transfer, –2 in 16-
bit transfer, –4 in 32-bit transfer; illegal setting in 16-byte
transfer)
1
Reserved (illegal setting)
Note: * This setting cannot be used to perform 16-byte transfers with a destination in X/Y memory.
If the transfer source is specified in indirect address, specify the address (indirect address) where
the address of data to be transferred is stored as data, in source address register 3 (SAR3).
Specification of SAR3 increment or decrement in indirect address mode depends on SM1 and
SM0 settings. In this case, however, the SAR3 increment or decrement value is +4, –4, or fixed to
0 regardless of the transfer data size specified in TS1 and TS0.
Rev. 5.00 Dec 12, 2005 page 390 of 1034
REJ09B0254-0500