SH7727 Datasheet, PDF (518/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 15 Timer (TMU)
15.2 TMU Registers
15.2.1 Timer Start Register (TSTR)
TSTR is an 8-bit read/write register that selects starting or stopping of the timer counters (TCNT)
for channels 0 to 2. TSTR is initialized to H'00 by a power-on reset or manual reset. TSTR is not
initialized in standby mode when the on-chip RTC clock (RTCCLK) is selected as the input clock
for the channel. However, only if the peripheral clock (Pφ) is selected for the channels, it is
initialized in standby mode when the multiplying ratio of PLL circuit 1 is modified and when the
MSTP2 bit in STBCR is set to 1.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
STR2 STR1 STR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W
R/W
R/W
Bits 7 to 3—Reserved: These bits are always read as 0 and should be written with 0.
Bit 2—Counter Start 2 (STR2): Selects starting or stopping of the timer counter 2 (TCNT2).
Bit 2: STR2
0
1
Description
Halts TCNT2 operation
Starts TCNT2 operation
(Initial value)
Bit 1—Counter Start 1 (STR1): starting or stopping of the timer counter 1 (TCNT1).
Bit 1: STR1
0
1
Description
Halts TCNT1 operation
Starts TCNT1 operation
(Initial value)
Bit 0—Counter Start 0 (STR0): Selects starting or stopping of the timer counter 0 (TCNT0).
Bit 0: STR0
0
1
Description
Halts TCNT0 operation
Starts TCNT0 operation
(Initial value)
Rev. 5.00 Dec 12, 2005 page 446 of 1034
REJ09B0254-0500