SH7727 Datasheet, PDF (698/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
Bit 1—Receive FIFO Under Run Enable (RFUDRE)
Bit 1: RFUDRE
0
1
Description
Disable interrupt of receive FIFO under run
Enable interrupt of receive FIFO under run (error interrupt)
Bit 0—Receive FIFO Over Run Enable (RFOVRE)
Bit 0: RFOVRE
0
1
Description
Disable interrupt of receive FIFO over run
Enable interrupt of receive FIFO over run (error interrupt)
20.2.10 Transmit Data Register (SITDR)
This register sets transmit data to SIOF. The data that has been set to this register is stored in
transmit FIFO. This register is initialized at power on reset, software reset, or transmit reset.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL SITDL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR SITDR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Bits 31 to 16—Transmit Data for Left Channel (SITDL15 to SITDL0): These bits set data
transmitted from TXD_SIO as left channel data. The position for left channel side data are
assigned as TDLA bit of SITDA register.
This bit becomes effective when 1 is set to TDLE bit of SITDAR register.
Bits 15 to 0—Transmit Data for Right Channel (SITDR15 to SITDR0): These bits set data
transmitted from TXD_SIO as right channel data. The position for left channel side data are
assigned as TDRA bit of SITDA register.
This bit becomes effective when 1 is set to TDRE bit of SITDAR register, and 0 is set to TLREP
bit of SITDAR register.
Rev. 5.00 Dec 12, 2005 page 626 of 1034
REJ09B0254-0500