SH7727 Datasheet, PDF (773/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
Bit 3—EP3 Stall (EP3 STL): When this bit is set to 1, endpoint 3 is placed in the stall state.
Bit 2—EP2 Stall (EP2 STL): When this bit is set to 1, endpoint 2 is placed in the stall state.
Bit 1—EP1 Stall (EP1 STL): When this bit is set to 1, endpoint 1 is placed in the stall state.
Bit 0—EP0 Stall (EP0 STL): When this bit is set to 1, endpoint 0 is placed in the stall state.
23.5.14 USB Interrupt Enable Register 0 (USBIER0)
USBIER0 enables the interrupt requests indicated in USB interrupt flag register 0 (USBIFR0).
When an interrupt flag is set while the corresponding bit in USBIER0 is set to 1, an interrupt
request is sent to the CPU. The contents of the interrupt event register (INTEVT2) are determined
by the contents of USB interrupt select register 0 (USBISR0).
Bit:
7
BRST
Initial value:
0
R/W: R/W
6
EP1
FULL
0
R/W
5
4
3
2
EP2
EP2 SETUP EP0o
TR EMPTY TS
TS
0
0
0
0
R/W
R/W
R/W
R/W
1
EP0i
TR
0
R/W
0
EP0i
TS
0
R/W
23.5.15 USB Interrupt Enable Register 1 (USBIER1)
USBIER1 enables the interrupt requests indicated in USB interrupt flag register 1 (USBIFR1).
When an interrupt flag is set while the corresponding bit in USBIER1 is set to 1, an interrupt
request is sent to the CPU. The contents of the interrupt event register (INTEVT2) are determined
by the contents of USB interrupt select register 1 (USBISR1).
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
EP3
EP3 VBUSF
TR
TS
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
23.5.16 USBEP1 Receive Data Size Register (USBEPSZ1)
USBEPSZ1 is the endpoint 1 receive data size register, indicating the amount of data received
from the host. The endpoint 1 FIFO buffer has a dual-FIFO configuration; the receive data size
indicated by this register refers to the currently selected FIFO.
Rev. 5.00 Dec 12, 2005 page 701 of 1034
REJ09B0254-0500