SH7727 Datasheet, PDF (505/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bit 1—Reserved: This is a readable/writable bit, but the write value should be always be 0.
Bit 0—Count start 0 (STR0): Selects whether the compare-match timer counter 0 is operated or
halted.
Bit 0: STR0
0
1
Description
CMCNT0 count operation is halted
CMCNT0 count operation is provided
(Initial value)
Compare-Match Timer Control/Status Register 0 (CMCSR0)
The compare-match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates a
compare-match occurrence and sets the incrementation clock. CMCSR0 is initialized to H'0000 by
a reset, but it retains its previous values in standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
CMF
—
—
—
—
—
CKS1 CKS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/W
R
R
R
R
R/W R/W
Note: * Only a 0 can be written, to clear the flag.
Bits 15 to 8 and 5 to 2—Reserved: These bits are always read as 0and should only be written
with 0.
Bit 7—Compare-Match Flag (CMF): This flag indicates that a compare-match of the compare-
match timer counter 0 (CMCNT0) and compare-match constant register 0 (CMCOR0) occurred.
Bit 7: CMF
0
1
Description
CMCNT0 and CMCOR0 have not matched
Clear condition: Write 0 to CMF after reading CMF = 1
A compare-match of CMCNT0 and CMCOR0 occurred
(Initial value)
Bit 6—Reserved: This is a readable/writable bit, but the write value should be always be 0.
Rev. 5.00 Dec 12, 2005 page 433 of 1034
REJ09B0254-0500