SH7727 Datasheet, PDF (314/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
Bit 3— USBH Reset (USBHR): When the USBH bit is set to 1, the USB host controller is reset.
0 should be written after writing 1.
Bit 3: USBHR
0
1
Description
Not reset USBH
Resets USBH
(Initial value)
Bit 2— LBSC Reset (LBSCR): When the LBSC bit is set to 1, the Li bus state controller (LBSC)
is reset. 0 should be written after writing 1.
Bit 2: LBSCR
0
1
Description
Not reset LBSC
Resets LBSC
(Initial value)
Bit 1— LCDC Reset (LCDCR): When the LCDC bit is set to 1, the LCD controller (LCDC) is
reset. 0 should be written after writing 1.
Bit 1: LCDCR
0
1
Description
Not reset LCDC
Resets LCDC
(Initial value)
Bit 0— PCC Reset (PCCR): When the PCC bit is set to 1, PC card controller (PCC) is reset. 0
should be written after writing 1.
Bit 0: PCCR
0
1
Description
Not reset PCC
Resets PCC
(Initial value)
Rev. 5.00 Dec 12, 2005 page 242 of 1034
REJ09B0254-0500