SH7727 Datasheet, PDF (784/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
(5) Status Stage (Control-Out)
USB function
IN token reception
Application
Valid data
in EP0i FIFO?
Yes
No
NACK
Interrupt request
0-byte transmission to host
ACK
Clear EP0i transfer-request
flag
(USBIFR0/EP0i TR = 0)
Write 1 to EP0i packet
enable bit
(USBTRG/EP0i PKTE = 1)
Set EP0i transfer-end flag
(USBIFR0/EP0i TS = 1)
Interrupt request
Clear EP0i transfer-end flag
(USBIFR0/EP0i TS = 0)
End of control transfer
End of control transfer
Figure 23.9 Status Stage Operation (Control-Out)
The status stage in control-out starts with in-token from the host. In in-token reception at the start
of status stage, an EP0o transfer-request interrupt occurs since no data is in EP0i FIFO. The
application acknowledges that the status stage has started by the interrupt. To transfer 0-byte data
to the host, no data is written to the EP0i FIFO, and 1 is written to the EP0i packet-enable bit.
Therefore, 0-byte data is transferred to the host in the next in-token, and control transfer is
completed.
However, after the application completes all processing related to the data stage, write 1 to the
EP0i packet-enable bit.
Rev. 5.00 Dec 12, 2005 page 712 of 1034
REJ09B0254-0500