SH7727 Datasheet, PDF (214/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 4 Exception Handling
To speed up TLB miss processing, the offset differs from other exceptions.
• TLB invalid exception
 Conditions: Comparison of TLB addresses shows address match but V = 0.
 Operations: The logical address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
The PC and SR of the instruction that generated the exception are saved in the SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
• TLB exception/CPU address error in repeat loop
 Conditions: TLB miss, TLB invalid or CPU address error in the last several instructions of
repeat loop (see section 3.5.6, MMU Exception in Repeat Loop)
 Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of
exception.
The SR of the instruction that generated the exception are saved in the SSR. But the SPC is not
the PC of the instruction that generated the exception. Repeat loop can not be restarted after
returning from exception handler. In order to complete a repeat loop, ensure not to cause TLB
exceptions or CPU address error in the last several instructions of repeat loop (see section
3.5.6, MMU Exception in Repeat Loop). If the TLB exception or CPU address error occurred
in the last several instructions of repeat loop, H'070 is set in EXPEVT. The BL, MD, and RB
bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
• Initial page write exception
 Conditions: A hit occurred to the TLB for a store access, but D = 0.
This occurs for initial writes to the page registered by the load.
 Operations: The logical address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bit in MMUCR.
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs in PC = VBR + H'0100.
Rev. 5.00 Dec 12, 2005 page 142 of 1034
REJ09B0254-0500