SH7727 Datasheet, PDF (861/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
25.2.19 LCDC Control Register (LDCNTR)
LDCNTR specifies start and stop of display by the LDCD.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
— DON2 —
—
— DON
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R
R
R R/W
Bits 15 to 1—Reserved
Bit 4— Display start auxiliary bit (DON2): Specifies the start of display operation using LCDC.
LCDC operation cannot be guaranteed if 0 is written to this bit at any time other than the start of
display operation. Note that a 1 written to this bit is automatically cleared to 0, so it is not
necessary to write 0 to it in order to clear it.
Bit 0—Display On (DON): Specifies the start and stop of the LCDC display operation.
The control sequence state can be checked by referencing the LPS value in bit 0 of the LCDC
power management mode register (LDPMMR).
Bit 4
DON2
0
1
Bit 0
DON
0
1
Description
Display-off mode: LCDC is stopped
Display-on mode: LCDC operates
(Initial value)
Starting LCDC Display Operation (DON2 and DON bits change from B'00 to B'11):
1. Start LCDC operation.
2. Turn on the LCD module following the sequence set in the LCDC power management mode
register (LDPMMR) and LCDC control register (LDCNTR).
The sequence ends when the LPS value changes from B'00 to B'11.
Do not make any action to the DON bit until the sequence ends.
Stopping LCDC Display Operation (DON2 and DON bits change from B'01 to B'00):
1. Turn off the LCD module following the sequence set in the LCDC power management mode
register (LDPMMR) and LCDC control register (LDCNTR).
2. Stop LCDC operation.
The sequence ends when the LPS value changes from B'11 to B'00.
Do not make any action to the DON bit until the sequence ends.
Rev. 5.00 Dec 12, 2005 page 789 of 1034
REJ09B0254-0500