SH7727 Datasheet, PDF(14/1109 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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SH7727 Datasheet, PDF (14/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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385 14.2.2 DMA Destination Address

Registers 0 to 3 (DAR0 to DAR3)

To transfer data in 16 bits or in 32 bits,

specify the address on the 16-bit or 32-bit

boundary. If any other address is specified,

correct operation is not guaranteed.

To transfer data in 16 bits or in 32 bits,

specify the address on the 16-bit or 32-bit

boundary. When transferring data in 16-

byte units, always set a value at a 16-byte

boundary (16n address) as the destination

address. If any other address is specified,

correct operation is not guaranteed.

433 14.4.2 Register Descriptions

Compare-Match Timer Control/Status

Register 0 (CMCSR0)

The compare-match timer control/status

register 0 (CMCSR0) is a 16-bit register

that indicates a compare-match

occurrence, sets enable/disable of

interrupts, and sets the incrementation

clock. â¦

The compare-match timer control/status

register 0 (CMCSR0) is a 16-bit register

that indicates a compare-match occurrence

and sets the incrementation clock. â¦

434 Bits 1 and 0ï£§clock Select 1, 0 (CKS1,

CKS0):

These bits select the clock input to CMCNT

from four internal clocks which are divided

from the system clock (PÏ). When the STR

bit in CMSTR is set to 1, â¦

These bits select the clock input to CMCNT

from four clocks which are divided from the

peripheral clock (PÏ). When the STR0 bit in

CMSTR is set to 1, â¦

Compare-Match Counter 0 (CMCNT0)

When the internal clock is selected with the When the clock is selected with the CKS1

CKS1 and CKS0 bits in CMCSR0 and the and CKS0 bits in CMCSR0 and the STR0

STR bit in CMSTR is set to 1, â¦

bit in CMSTR is set to 1, â¦

435 14.4.3 Operation

Period Count Operation

When the internal clock is selected with the When the clock is selected with the CKS1

CKS1, CKS0 bits in CMCSR0 and the STR and CKS0 bits in CMCSR0 and the STR0

bit of the CMSTR is set to 1,

bit in CMSTR is set to 1, â¦

Rev. 5.00 Dec 12, 2005 page xiv of lxxii

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