SH7727 Datasheet, PDF (855/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
25.2.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the timing of the generation of the vertical (scan direction and vertical
direction) sync signals (FLM/Vsync) for the LCD module.
Bit: 15
14
13
12
VSYN VSYN VSYN VSYN
W3 W2 W1 W0
Initial value: 0
0
0
0
R/W: R/W R/W R/W R/W
11
10
9
8
7
6
5
4
3
2
1
0
— VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
1
0
1
1
1
1
1
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 11—Reserved
Bits 15 to 12—Vertical Sync Signal Width (VSYNW): Set the width of the vertical sync signals
(FLM and Vsync) (unit: line).
Subtract 2 from the setting (0 to 15 (H'F)).
Example: For a vertical sync signal width of 1 line
VSYNW = (1 – 1) = 0 = H'0
Bits 10 to 0— Vertical Sync Signal Output Position (VSYNP): Set the output position of the
vertical sync signals (FLM and Vsync) (unit: line).
Subtract 2 from the setting (0 to 2046 (H'7FE)).
DSTN should be set to an odd number value. It is handled as (setting value + 1)/ 2.
Example: For an 480-line LCD module and a vertical retrace period of 0 lines (in other words,
VTLN = 479 and the vertical sync signal is active for the first line):
• Single display
VSYNP=[(1-1)+VTLN] mod (VTLN+1) = [(1-1)+479] mod (479+1)
= 479 mod 480 = 479
= H'1DF
• Dual displays
VSYNP=[(1-1)×2+VTLN] mod (VTLN+1) = [(1-1)×2+479] mod (479+1)
= 479 mod 480 = 479
= H'1DF
Rev. 5.00 Dec 12, 2005 page 783 of 1034
REJ09B0254-0500