SH7727 Datasheet, PDF (463/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bits 11 to 8—Resource 3 to 0 (RS3 to RS0): RS3 to RS0 specify which transfer requests will be
sent to the DMAC.
Bit 11: Bit 10: Bit 9: Bit 8:
RS3 RS2 RS1 RS0 Description
0
0
0
0
External request^*1, dual address mode
(Initial value)
1
Illegal setting
1
0
External request^*1/Single address mode
External address space → external device with DACK
1
External request^*1/Single address mode
External device with DACK → external address space
1
0
0
Auto request
1
Illegal setting
1
0
Illegal setting
1
Illegal setting
1
0
0
0
Select DMA request expansion^*3
1
Illegal setting
1
0
Illegal setting
1
Illegal setting
1
0
0
SCIF transmission^*2
1
SCIF reception^*2
1
0
Internal A/D^*2
1
CMT^*2
Notes: 1. External request specification is valid only for channels 0. None of the request sources
can be selected for channels 1, 2 and 3.
2. When using 16-byte transfer, the following settings must not be made:
1100 SCIF transmission
1101 SCIF reception
1110 A/D converter
1111 CMT
Operation is not guaranteed if these settings are made.
3. When DMA transfer is provided with the USB function controller or SIOF, set RS3 to
RS0 to 1000 and select a desired module with the CHRAR register.
Rev. 5.00 Dec 12, 2005 page 391 of 1034
REJ09B0254-0500