SH7727 Datasheet, PDF (356/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
• Refresh function
 Refresh cycles will be automatically maintained in the sleep mode even after the external
bus frequency is reduced to 1/4 of its normal operating frequency
• The refresh counter can be used as an interval timer
 Outputs an interrupt request signal using the compare-matching function
 Outputs an interrupt request signal when the refresh counter overflows
• Automatically disables the output of clock signals to anywhere but the refresh counter, except
during execution of external bus cycles
Note: * PCMCIA direct interface supported by the BSC is only signals and bus protocols shown
in table 12.5. For details on other control signals, refer to section 30, PC Card Controller
(PCC) (external circuit and this LSI on-chip card controller. In this BSI, both areas 5 and
6 has PCMICIA direct interface function common to the SH3 Series. The on-chip PC
Card Controller supports only area 6.
Rev. 5.00 Dec 12, 2005 page 284 of 1034
REJ09B0254-0500