SH7727 Datasheet, PDF (682/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
Bit 5—Transmit or Receive Control Command Interrupt Mode (RCIM)
Bit 5: RCIM
0
1
Description
Set RCRDY bit of SISTR register when the contents of SIRCR register is
changed.
(Initial value)
Set RCRDY bit of SISTR register when every control commands are received
and set to SIRCR register
20.2.2 Clock Select Register (SISCR)
This register sets the operate of baud rate generator. To set up this register, TRMD bit of SIMDR
register must be set 10 or 11.
This register is initialized in power on reset or software reset.
Bit: 15
14
13
12
11
10
9
8
MSSEL MSIMM
—
BRPS4 BRPS3 BRPS2 BRPS1 BRPS0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R*
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
BRDV2 BRDV1 BRDV0
Initial value:
0
0
0
0
0
0
0
0
R/W: R*
R*
R*
R*
R*
R/W
R/W
R/W
Note: * 0 must be written into this bit. The operation of this LSI is unpredictable when setting the
value other than 0.
Bit 15—Master Clock Source Choice (MSSEL): Master clock means the clock that is input to
the baud rate generator.
Bit 15: MSSEL
0
1
Description
Use external clock source SIOMCLK input signal as master clock(Initial value)
Use peripheral clock (Pφ) as master clock
Rev. 5.00 Dec 12, 2005 page 610 of 1034
REJ09B0254-0500