SH7727 Datasheet, PDF (260/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
When using edge sensing for IRQ interrupts, do the following to clear IR0.
To clear bits IRQ5R to IRQ0R to 0, read from IRR0 before writing. After confirming that the bits
to be cleared to 0 are set to 1, write 0 to them. In this case write 0 only to the bits to be cleared;
write 1 to the other bits. The values of the bits to which 1 is written do not change.
When level sensing is used for IRQ interrupts, bits IRQ5R to IRQ0R indicate whether or not an
interrupt request has been input. They can be set and cleared by the values input to pins IRQ5R to
IRQ0R alone.
Bit 7—PINT0 to PINT7 Interrupt Request (PINT0R): Indicates whether interrupt requests are
input to PINT0 to PINT7 pins.
Bit 7: PINT0R
0
1
Description
Interrupt requests are not input to PINT0 to PINT7 pins
Interrupt requests are input to PINT0 to PINT7 pins.
(Initial value)
Bit 6—PINT8 to PINT15 Interrupt Request (PINT1R): Indicates whether interrupt requests are
input to PINT8 to PINT15 pins.
Bit 6: PINT1R
0
1
Description
Interrupt requests are not input to PINT8 to PINT15 pins
Interrupt requests are input to PINT8 to PINT15 pins.
(Initial value)
Bit 5—IRQ5 Interrupt Request (IRQ5R): Indicates whether an interrupt request is input to the
IRQ5 pin. When edge detection mode is set for IRQ5, an interrupt request is cleared by clearing
the IRQ5R bit.
Bit 5: IRQ5R
0
1
Description
An interrupt request is not input to IRQ5 pin
An interrupt request is input to IRQ5 pin
(Initial value)
Rev. 5.00 Dec 12, 2005 page 188 of 1034
REJ09B0254-0500