SH7727 Datasheet, PDF (918/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 27 I/O Ports
27.2 Register Configuration
Table 27.1 summarizes the registers of the pin function controller.
Table 27.1 Pin Function Controller Registers
Name
Abbreviation R/W
Initial Value Address
Access Size
Port A data register PADR
R/W
H'00
H'04000120
8
(H'A4000120)^*1
Port B data register PBDR
R/W
H'00
H'04000122
8
(H'A4000122)^*1
Port C data register PCDR
R/W
H'00
H'04000124
8
(H'A4000124)^*1
Port D data register PDDR
R/W or R B'0*0*0000 H'04000126
8
(H'A4000126)^*1
Port E data register PEDR
R/W
H'00
H'04000128
8
(H'A4000128)^*1
Port F data register PFDR
R
H'**
H'0400012A
8
(H'A400012A)^*1
Port G data register PGDR
R
H'**
H'0400012C
8
(H'A400012C)^*1
Port H data register PHDR
R/W or R B'0*******
H'0400012E
8
(H'A400012E)^*1
Port J data register PJDR
R/W
H'00
H'04000130 8
(H'A4000130)^*1
Port K data register PKDR
R/W
H'00
H'04000132
8
(H'A4000132)*
Port L data register PLDR
R
H'**
H'04000134
8
(H'A4000134)^*1
SC port data register SCPDR
R/W or R B'*0000000
H'04000136
8
(H'A4000136)^*1
Port M data register PMDR
R
B'********
H'04000138
8
(H'A4000138)^*1
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
* Means no value.
1. When address translation by the MMU does not apply, the address in parentheses
should be used.
Rev. 5.00 Dec 12, 2005 page 846 of 1034
REJ09B0254-0500