SH7727 Datasheet, PDF (659/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 3—Modem Control Enable (MCE): Enables the modem control signals CTS and RTS.
Bit 3: MCE
Description
0
Disables the modem signal*
(Initial value)
1
Enables the modem signal
Note: * The CTS is fixed to active 0 regardless of the input value, and the RTS is also fixed to 0.
Bit 2—Transmit FIFO Data Register Reset (TFRST): Disables the transmit data in the transmit
FIFO data register 2 and resets the data to the empty state.
Bit 2: TFRST Description
0
Disables reset operation*
1
Enables reset operation
Note: * Reset is operated in resets or the standby mode.
(Initial value)
Bit 1—Receive FIFO Data Register Reset (RFRST): Disables the receive data in the receive
FIFO data register 2 and resets the data to the empty state.
Bit 1: RFRST Description
0
Disables reset operation*
1
Enables reset operation
Note: * Reset is operated in resets or the standby mode.
(Initial value)
Bit 0—Loop Back Test (LOOP): Internally connects the transmit output pin (TXD2) and receive
input pin (RXD2) and enables the loop back test.
Bit 0: LOOP
0
1
Description
Disables the loop back test
Enables the loop back test
(Initial value)
Rev. 5.00 Dec 12, 2005 page 587 of 1034
REJ09B0254-0500