SH7727 Datasheet, PDF (772/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
23.5.12 USB Data Status Register (USBDASTS)
USBDASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set when data
is written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all
data has been transmitted to the host.
Bit:
7
6
5
4
3
2
1
0
—
—
EP3
EP2
—
—
—
EP0i
DE
DE
DE
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 5—EP3 Data Present (EP3 DE): This bit is set when the endpoint 3 FIFO buffer contains
valid data.
Bit 4—EP2 Data Present (EP2 DE): This bit is set when the endpoint 2 FIFO buffer contains
valid data.
Bits 3 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—EP0i Data Present (EP0i DE): This bit is set when the endpoint 0 FIFO buffer contains
valid data.
23.5.13 USB Endpoint Stall Register (USBEPSTL)
The bits in USBEPSTL are used to forcibly stall the endpoints on the application side. While a bit
is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for
endpoint 0 (EP0 STL) is cleared automatically on reception of 8-bit command data for which
decoding is performed by the function. When the SETUPTS flag in USB interrupt flag register 0 is
set, a write of 1 to the EP0 STL bit is ignored. For details see section 23.8, Stall Operations.
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
EP3
EP2
EP1
EP0
STL
STL
STL
STL
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R/W
R/W
R/W
R/W
Bits 7 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.00 Dec 12, 2005 page 700 of 1034
REJ09B0254-0500