SH7727 Datasheet, PDF (11/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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265, Table 10.4 Available Combination of Clock
266 Mode and FRQCR Values
Cautions:
1. The frequency ranges of the input clock and crystal
oscillator should be set within the specified frequency
range based on the clock rate in table 10.4, and section
32.3, AC Characteristics.
2. The input to divider 1 becomes the output of:
• PLL circuit 1 when PLL circuit 1 is on.
• PLL circuit 2 when PLL circuit 1 is off and PLL circuit 2
is on.
3. The input of divider 2 becomes the output of:
• PLL circuit 1
4. The frequency of the internal clock (Iφ) becomes:
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 1 when PLL circuit 1 is on.
• Equal to the frequency of CKIO pin when PLL circuit 1
is off.
• Do not set the internal clock frequency lower than the
CKIO pin frequency.
5. The frequency of the peripheral clock (Pφ) becomes:
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 2 when the clock operating mode
is 0 to 2 or 7.
• The peripheral clock frequency should not be set
higher than the maximum frequency specified in the AC
Characteristics, higher than the frequency of the CKIO
pin, higher than 40 MHz, or lower than 1/8 the internal
clock (Iφ).
6. The output frequency of PLL circuit 1 is the product of
the CKIO frequency and the multiplication ratio of PLL
circuit 1. This frequency should be equal to or lower
than the maximum frequency specified in the AC
Characteristics.
7. × 1, × 2, × 3, × 4, or × 6 can be used as the
multiplication ratio of PLL circuit 1. × 1, × 1/2, × 1/3, and
× 1/4 can be selected as the division ratio of divider 1.
× 1, × 1/2, × 1/3, × 1/4, and × 1/6 can be selected as the
division ratio of divider 2. Set the rate in the frequency
control register. The on/off state of PLL circuit 2 is
determined by the mode.
Cautions:
1. The frequency ranges of the input clock and crystal
oscillator should be set within the specified frequency
range based on the clock rate in table 10.4, and section
32.3, AC Characteristics.
2. The input to divider 1 becomes the output of PLL
circuit 1 when PLL circuit 1 is on.
3. The input of divider 2 becomes the output of:
• PLL circuit 1
4. The frequency of the internal clock (Iφ) becomes:
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 1 when PLL circuit 1 is on.
• Do not set the internal clock frequency lower than the
CKIO pin frequency.
• Depending on the product, the clock ratio should be
set to produce a frequency within one of the ranges
indicated below.
100 MHz products: 24 MHz to 100 MHz
160 MHz products: 24 MHz to 160 MHz
5. Bus clock (Bφ) frequency:
• Depending on the product, the clock ratio should be
set to produce a frequency within one of the ranges
indicated below.
100 MHz products: 24 MHz to 50 MHz
160 MHz products: 24 MHz to 66.64 MHz
6. The frequency of the peripheral clock (Pφ) becomes:
• The product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1, and the
division ratio of divider 2.
• For all products, the peripheral clock frequency (Pφ)
should be set within the frequency range 6 MHz to
33.34 MHz and no higher than the frequency of the
CKIO pin.
• The peripheral clock frequency (Pφ) should be set to
13 MHz or higher if the USB function module is used.
7. The output frequency of PLL circuit 1 is the product of
the CKIO frequency and the multiplication ratio of PLL
circuit 1.
8. ×1, ×2, ×3, ×4, or ×6 can be used as the multiplication
ratio of PLL circuit 1. ×1, ×1/2, ×1/3, and ×1/4 can be
selected as the division ratio of divider 1. ×1, ×1/2, ×1/3,
×1/4, and ×1/6 can be selected as the division ratio of
divider 2. Set the rate in the frequency control register.
The on/off state of PLL circuit 2 is determined by the
mode.
Rev. 5.00 Dec 12, 2005 page xi of lxxii