SH7727 Datasheet, PDF (513/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.6 Usage Notes
1. The DMA channel control registers (CHCR0 to CHCR3) can be accessed with any data size.
The DMA operation register (DMAOR) must be accessed in byte (8 bits) or word (16 bits)
units; other registers must be accessed in word (16 bits) or longword (32 bits) units.
2. When modifying the RS0 to RS3 bits in CHCR0 to CHCR3, first clear the DE bit to 0 (when
modifying CHCR with a byte address, be sure to set the DE bit to 0 in advance).
3. If an NMI interrupt is input when the DMAC is not operating, the NMIF bit of the DMAOR is
set.
4. A transition to standby mode should be made after the DME bit in DMAOR is cleared to 0 and
the transfers that has been accepted by the DMAC end.
5. The on-chip supporting modules that the DMAC can access are, SIOF, SCIF, USB function,
A/D converter, and I/O ports. Do not access the other on-chip supporting modules by the
DMAC.
6. When starting up the DMAC, set CHCR or DMAOR last. Specifying other registers last does
not guarantee normal operation.
7. When the DMA transfer ends normally and subsequently the maximum number of transfers is
performed in the same channel, write 0 to DMATCR. Otherwise, normal DMA transfer may
not be performed.
8. When using the address reload function, specify the burst mode for the transfer mode. In the
cycle-steal mode, normal DMA transfer may not be performed.
9. When using the address reload function, set a multiple of four to DMATCR. Specifying other
values does not guarantee normal operation.
10. When detecting an external request at the falling edge, keep the external request pin high when
setting the DMAC.
11. Do not access the space from H'4000062 to H'400006F, which is not used by the DMAC.
Accessing that space may cause malfunctions.
12. The WAIT signal is ignored when writing to an external address area using DMA 16-byte
transfer in dual address mode, and also when transferring data from a DACK-equipped
external device to an external address area using DMA 16-byte transfer in single address
mode.
13. Big-endian access is used when transferring data from XY memory using the DMAC if all of
the following conditions are met:
Conditions:
(1) Transfer source address in XY memory
(2) Indirect addressing mode
(3) Byte size data
(4) Little-endian data transfer
Rev. 5.00 Dec 12, 2005 page 441 of 1034
REJ09B0254-0500