SH7727 Datasheet, PDF (686/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
Bits 11 to 8—Receive Data for Left Channel Slot Assignment (RDLA3 to RDLA0): The slot
assignment of received data for left channel in received frame is specified from 0000(0: initial
value) to 1110(14) by this register. The receive data for left channel is stored in bits 15 to 0 in
SIRDL of SIRDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits RDLA3 to RDLA0.
Bit 7—Receive Data for Right Channel Enable (RDRE)
Bit 7: RDRE
0
1
Description
Disable receiving of right channel data
Enable receiving of right channel data
(Initial value)
Bits 3 to 0—Receive Data for Right Channel Slot Assignment (RDRA3 to RDRA0): The slot
assignment of received data for right channel in received frame is specified from 0000(0: initial
value) to 1110(14) by this register. The receive data for right channel is stored in bits 15 to 0 in
SIRDR of SIRDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits RDRA3 to RDRA0.
20.2.5 Control Command Assign Register (SICDAR)
This register specifies the position of control command in each frame. The setting to this register
is enabled when 1*** is set to bits FL3 to FL0 of SIMDR register. This register is initialized at
power on reset or software reset.
Bit: 15
14
13
12
11
10
9
8
CD0E
—
—
—
CD0A3 R/W2 R/W1 R/W0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
CD1E
—
—
—
CD1A3 CD1A2 CD1A1 CD1A0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R/W
R/W
R/W
R/W
Bits 14 to 12, and 6 to 4—Reserved
Rev. 5.00 Dec 12, 2005 page 614 of 1034
REJ09B0254-0500