SH7727 Datasheet, PDF (196/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
(4) 4 or more instructions repeated (inst1, inst2, ..., instN, SR.RC=2)
inst-1 IF
inst0
inst1
inst2
:
instN-3
instN-2
instN-1
instN
inst1
inst2
:
instN-3
instN-2
instN-1
instN
instN+1
ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
:
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
:
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
: Exception source stage where SPC is not correct
and repeat loop can not be restarted
Figure 3.14 MMU Exception in Repeat Loop (cont)
3.6 Memory-Mapped TLB
In order for TLB operations to be managed by software, TLB contents can be read or written to in
the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the logical
address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to
H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to
H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only
longword access is possible for both the address array and the data array.
Rev. 5.00 Dec 12, 2005 page 124 of 1034
REJ09B0254-0500