SH7727 Datasheet, PDF (487/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
DREQ
Bus right returned to CPU
Bus cycle
CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU
Read Write
Read Write
Figure 14.14 Transfer Example in Cycle-Steal Mode
• Burst Mode
Once the DMAC obtains the bus right, the transfer is continued until the transfer end condition is
satisfied. However, when the DREQ pin is driven high in the external request mode with low level
detection of the DREQ pin, the bus right is passed to the other bus master after the DMA transfer
request that has already been accepted ends, even if the transfer end condition has not been
satisfied.
The burst mode cannot be used when the transfer request source is set to the serial
communications interface with FIFO (SCIF). Figure 14.15 shows a timing of the DMA transfer
operation in the burst mode.
DREQ
Bus cycle
CPU
CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read Write Read Write Read Write
Figure 14.15 Example of Transfer in Burst Mode
Relationship between Request Mode and Bus Mode: Table 14.6 shows the relationship between
request mode and bus mode for each combination of DMA transfer areas.
Rev. 5.00 Dec 12, 2005 page 415 of 1034
REJ09B0254-0500