SH7727 Datasheet, PDF (688/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.2.6 Serial Control Register (SICTR)
This register sets the operating states of SIOF.
This register is initialized at power on reset or software reset.
Bit: 15
14
13
12
11
SCKE FSE
—
—
—
Initial value:
0
0
0
0
0
R/W: R/W
R/W
R
R
R
10
9
8
—
TXE
RXE
0
0
0
R
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
TXRST RXRST
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
W
W
Bits 13 to 10, and 7 to 2—Reserved
Bit 15—Serial Clock Output Enable (SCKE): This bit is effective in master mode. When 1 is
set to this bit, SIOF initializes baud rata generator, then starts, operation, and outputs the clock that
is generated by baud rate generator to SCK_SIO.
Bit 15: SCKE
0
1
Description
Disable output of SCK_SIO (outputs 0)
Enable output of SCK_SIO
(Initial value)
Bit 14—Frame Synchronize Signal Output Enable (FSE): This bit is effective at master mode.
When 1 is set to this bit, SIOF initializes the frame counter, then starts operation.
Bit 14: FSE
0
1
Description
Disable output of SIOFSYNC (outputs 0)
Enable output of SIOFSYNC
(Initial value)
Rev. 5.00 Dec 12, 2005 page 616 of 1034
REJ09B0254-0500