SH7727 Datasheet, PDF (180/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
Virtual address
31
17 16 12 11
0
Index
Ways 0 to 3
0 VPN(31−17) VPN(11−10) ASID(7−0) V PPN(31−10) PR(1−0) SZ C D SH
31
Address array
Data array
Figure 3.7 TLB Indexing (IX = 0)
3.3.3 TLB Address Comparison
A TLB address comparison is performed when an instruction is fetched from a program in
external memory or data in external memory is referenced. The items used in the comparison are
VPN and ASID. The VPN of the logical address that accesses external memory is compared to the
VPN of the TLB entry selected with the index number. The ASID within the PTEH is compared to
the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the compared
values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered.
It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one
way, as hardware operation is not guaranteed if this occurs. For example, if there are two identical
TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a
process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the non-shared
state (SH = 0), then if the ASID in PTEH is set to H'FF, there is a possibility of simultaneous TLB
hits in both these ways. It is therefore necessary to ensure that this kind of setting is not made by
software.
The object compared varies depending on the page management information (SZ, SH) in the TLB
entry. It also varies depending on whether the system supports multiple virtual memory or single
virtual memory.
Rev. 5.00 Dec 12, 2005 page 108 of 1034
REJ09B0254-0500