SH7727 Datasheet, PDF (838/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
Register Name
Abbreviation Initial Value Address
Access Size
LCDC fetch data line address offset
register for display panel
LDLAOR
H’0280
H’04000C10
16
(H’A4000C10)*
LCDC palette control register
LDPALCR
H’0000
H’04000C12
16
(H’A4000C12)*
LCDC palette data registers 00 to FF
LDPR00–FF
Undefined
H’04000800 to 32
H’04000BFC
(H’A4000800 to
H’A4000BFC)*
LCDC horizontal character number
register
LDHCNR
H’4F52
H’04000C14
16
(H’A4000C14)*
LCDC horizontal synchronization signal LDHSYNR
register
H’0050
H’04000C16
16
(H’A000C16)*
LCDC vertical displayed line number
register
LDVDLNR
H’01DF
H’04000C18
16
(H’A4000C18)*
LCDC vertical total line number register LDVTLNR
H’01DF
H’04000C1A
16
(H’A4000C1A)*
LCDC vertical synchronization signal
register
LDVSYNR
H’01DF
H’04000C1C
16
(H’A4000C1C)*
LCDC ac modulation signal toggle line LDACLNR
number register
H’000C
H’04000C1E
16
(H’A4000C1E)*
LCDC interrupt control register
LDINTR
H’0000
H’04000C20
16
(H’A4000C20)*
LCDC power management mode
register
LDPMMR
H’0010
H’04000C24
16
(H’A4000C24)*
LCDC power supply sequence period
register
LDPSPR
H’F60F
H’04000C26
16
(H’A4000C26)*
LCDC control register
LDCNTR
H’0000
H’04000C28
16
(H’A4000C28)*
Note: * When the LCDC is not a target for address conversion by the MMU, use the addresses in parentheses.
Rev. 5.00 Dec 12, 2005 page 766 of 1034
REJ09B0254-0500