SH7727 Datasheet, PDF (262/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Bit 0: IRQ0R
0
1
Description
An interrupt request is not input to IRQ0 pin
An interrupt request is input to IRQ0 pin
(Initial value)
7.3.8 Interrupt Request Register 1 (IRR1)
The IRR1 is an 8-bit read-only register that indicates whether DMAC or interrupt requests are
generated. This register is initialized to H'00 at power-on reset or manual reset, but is not
initialized in standby mode.
Bit: 7
6
5
4
3
2
1
0
—
—
—
— DEI3R DEI2R DEI1R DEI0R
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 7 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—DEI3 Interrupt Request (DEI3R): Indicates whether a DEI3 (DMAC) interrupt request
is generated.
Bit 3: DEI3R
0
1
Description
A DEI3 interrupt request is not generated
A DEI3 interrupt request is generated
(Initial value)
Bit 2—DEI2 Interrupt Request (DEI2R): Indicates whether a DEI2 (DMAC) interrupt request
is generated.
Bit 2: DEI2R
0
1
Description
A DEI2 interrupt request is not generated
A DEI2 interrupt request is generated
(Initial value)
Bit 1—DEI1 Interrupt Request (DEI1R): Indicates whether a DEI1 (DMAC) interrupt request
is generated.
Bit 1: DEI1R
0
1
Description
A DEI1 interrupt request is not generated
A DEI1 interrupt request is generated
(Initial value)
Rev. 5.00 Dec 12, 2005 page 190 of 1034
REJ09B0254-0500