SH7727 Datasheet, PDF (370/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
12.2.3 Wait State Control Register 1 (WCR1)
Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of
idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may
not be turned off quickly even when the read signal from the external device is turned off. This
can result in conflicts between data buses when consecutive memory accesses are to different
memories or when a write immediately follows a memory read. This LSI automatically inserts idle
states equal to the number set in WCR1 in those cases.
WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by
standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
WAIT — A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 —
SEL
IW1 IW0 IW1 IW0 IW1 IW0 IW1 IW0 IW1 IW0
Initial value: 0
0
1
1
1
1
1
1
1
1
1
1
0
R/W: R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
2
1
0
— A0 A0
IW1 IW0
0
1
1
R R/W R/W
Bit 15—WAIT Sampling Timing Select (WAITSEL): Specifies the WAIT signal sampling
timing.
Bit 15: WAITSEL Description
0
Set to 1 when WAIT signal is used.*
(Initial value)
1
Sampled at the falling edge of CKIO.
Note: * If low level is input to the WAIT by setting the WAITSEL bit, the LSI operation cannot be
guaranteed.
Bits 14, 3, and 2 —Reserved: These bits are always read as 0. The write value should always be
0.
Rev. 5.00 Dec 12, 2005 page 298 of 1034
REJ09B0254-0500