SH7727 Datasheet, PDF (588/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0, the SCI
recognizes that the transmit data register (SCTDR) contains new data, and loads this data from
the SCTDR into the transmit shift register (SCTSR).
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the
SCSCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: One 0 bit is output.
b. Transmit data: Seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor
bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can
also be selected.
d. Stop bit: One or two 1 bits (stop bits) are output.
e. Marking: Output of 1 bits continues until the start bit of the next transmit data.
3. The SCI checks the TDRE bit when it outputs the stop bit.
If TDRE is 0, the SCI loads new data from the SCTDR into the SCTSR, outputs the stop bit,
then begins serial transmission of the next frame.
If TDRE is 1, the SCI sets the TEND bit to 1 in the SCSSR, outputs the stop bit, then continues
output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set
to 1, a transmit-end interrupt (TEI) is requested.
Figure 17.9 shows an example of SCI transmit operation in the asynchronous mode.
Rev. 5.00 Dec 12, 2005 page 516 of 1034
REJ09B0254-0500