SH7727 Datasheet, PDF(217/1109 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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SH7727 Datasheet, PDF (217/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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Section 4 Exception Handling

ï£§ Operations: The PC and SR of the instruction that generated the exception are saved to the

SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are

set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other

than H'Fxxx is decoded, operation cannot be guaranteed.

â¢ Illegal slot instruction

ï£§ Conditions:

a. When undefined code in a delay slot is decoded

Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,

BF/S, Undefined instruction: H'Fxxx

b. When an instruction that rewrites the PC in a delay slot is decoded

Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT,

BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR

c. When a privileged instruction in a delay slot is decoded in user mode

Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access

GBR with LDC/STC are not privileged instructions.

d. When a DSP instruction in a delay slot is decoded without DSP extension (SR.DSP=0)

DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,

DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L

DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,

STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS,

MOVX, MOVY, Pxxx

ï£§ Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the

instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL,

MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an

undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed.

â¢ User break point trap

ï£§ Conditions: When a break condition set in the user break controller is satisfied

ï£§ Operations: When a post-execution break occurs, the PC of the instruction immediately

after the instruction that set the break point is set in the SPC. If a pre-execution break

occurs, the PC of the instruction that set the break point is set in the SPC. SR when the

break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are

set to 1 and a branch occurs to PC = VBR + H'0100. See section 8, User Break Controller

(UBC), for more information.

Rev. 5.00 Dec 12, 2005 page 145 of 1034

REJ09B0254-0500

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