SH7727 Datasheet, PDF (506/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to CMCNT
from four clocks which are divided from the peripheral clock (Pφ). When the STR0 bit in CMSTR
is set to 1, the CMCNT0 starts incrementation with the clock selected by CKS1 and CKS0.
Bit 1: CKS1
0
1
Bit 0: CKS0
0
1
0
1
Description
Pφ/4
Pφ/8
Pφ/16
Pφ/64
(Initial value)
Compare-Match Counter 0 (CMCNT0)
The compare-match counter 0 (CMCNT0) is a 16-bit register that is used as an up-counter.
When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in
CMSTR is set to 1, CMCNT0 starts incrementation with the selected clock. When the CMCNT0
value matches that in the compare-match constant register 0 (CMCOR0), the CMCNT0 is cleared
to H'0000 and the CMF flag in CMCSR0 is set to 1.
CMCNT0 is initialized to H'0000 by a reset, but it retains its previous values in standby mode.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 434 of 1034
REJ09B0254-0500