SH7727 Datasheet, PDF (215/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 4 Exception Handling
• TLB protection exception
 Conditions: When a hit access violates the TLB protection information (PR bits) shown
below:
PR
Privileged mode
User mode
00
Only read enabled No access
01
Read/write enabled No access
10
Only read enabled Only read enabled
11
Read/write enabled Read/write enabled
 Operations: The logical address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception
occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
• TLB protection violation in repeat loop
 Conditions: TLB protection violation in the last several instruction of repeat loop (see
section 3.5.6, MMU Exception in Repeat Loop)
 Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of
exception.
The SR of the instruction that generated the exception are saved in the SSR. But the SPC is not
the PC of the instruction that generated the exception. Repeat loop can not be restarted after
returning from exception handler. In order to complete a repeat loop, ensure not to cause TLB
exceptions or CPU address error in the last several instructions of repeat loop (see section
3.5.6, MMU Exception in Repeat Loop). If a TLB protection violation occurs in an instruction
immediately before or during a repeat loop, H'0D0 is set in EXPEVT. The BL, MD, and RB
bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
• CPU Address error
 Conditions:
a. Instruction fetch from odd address (4n + 1, 4n + 3)
b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF.
Rev. 5.00 Dec 12, 2005 page 143 of 1034
REJ09B0254-0500