SH7727 Datasheet, PDF (587/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Serial Data Transmission (Asynchronous Mode):
Figure 17.8 shows a sample flow chart for serial data transmission. After enabling the SCI
transmission, transmit serial data following the procedure shown below:
Start transmission
Read TDRE bit in SCSSR
(1)
No
TDRE = 1?
Yes
Write transmission data to
SCTDR and clear TDRE bit in
SCSSR to 0
(2)
All data transmitted?
No
Yes
Read TEND bit in SCSSR
TEND = 1?
No
Yes
No
Break output?
Yes
(3)
Set SCPDR and SCPCR
Clear TE bit SCSCR to 0
(1) SCI status check and transmit data
write:
Read the serial status register
(SCSSR), check that the TDRE bit is 1,
then write transmit data in the transmit
data register (SCTDR) and clear TDRE
to 0.
(2) To continue transmitting serial data:
Read the TDRE bit to check whether it
is safe to write (if it reads 1); if so, write
data in SCTDR, then clear TDRE to 0.
(3) To output a break at the end of serial
transmission:
Set the SC port data register (SCPDR)
and SC port control register (SCPCR),
then clear the TE bit to 0 in the serial
control register (SCSCR). For SCPCR
and SCPDR settings, see section
17.2.8, Port SC Control Register
(SCPCR)/Port SC Data Register
(SCPDR).
End transmission
Figure 17.8 Sample Serial Transmission Flowchart
Rev. 5.00 Dec 12, 2005 page 515 of 1034
REJ09B0254-0500