SH7727 Datasheet, PDF(213/1109 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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SH7727 Datasheet, PDF (213/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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Section 4 Exception Handling

â¢ Manual Reset

ï£§ Conditions: RESETM low

ï£§ Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000.

Initialization sets the VBR register to H'00000000. In SR, the MD, RB, and BL bits are set

to 1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting

modules are initialized. See the register descriptions in the relevant sections for details. A

high level is output from the STATUS0 and STATUS1 pins.

â¢ H-UDI Reset

ï£§ Conditions: H-UDI reset command input (see section 31.4.3, H-UDI Reset)

ï£§ Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.

Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to

1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting

modules are initialized. See the register descriptions in the relevant sections for details.

Table 4.4 Types of Reset

Type

Power-on

reset

Manual

reset

H-UDI

reset

Conditions for Transition

to Reset State

RESETP = Low

RESETM = Low

H-UDI reset command input

CPU

Initialized

Initialized

Initialized

Internal State

On-Chip Supporting Modules

(See register configuration in

relevant sections)

4.5.2 General Exceptions

â¢ TLB miss exception

ï£§ Conditions: Comparison of TLB addresses shows no address match

ï£§ Operations: The logical address (32 bits) that caused the exception is set in TEA and the

corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH

indicates the ASID at the time the exception occurred. The RC bit in MMUCR is

incremented by 1 when all ways are enabled, and if there is a disabled way, setting is

prioritized starting from way 0.

The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception

occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1

and a branch occurs to PC = VBR + H'0400.

Rev. 5.00 Dec 12, 2005 page 141 of 1034

REJ09B0254-0500

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