SH7727 Datasheet, PDF (619/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 18 Smart Card Interface
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0: SMIF
0
1
Description
Smart card interface function disabled
Smart card interface function enabled
(Initial value)
18.2.2 Serial Status Register (SCSSR)
In the smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions
for bit 2, the TEND bit, are also changed.
Bit: 7
6
5
4
3
TDRE RDRF ORER FER/ERS PER
Initial value: 1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Bits 7 to 5—These bits have the same function as in the ordinary SCI. See section 17, Serial
Communication Interface (SCI), for more information.
Bit 4—Error Signal Status (ERS): In the smart card interface mode, bit 4 indicates the state of
the error signal returned from the receiving side during transmission. The smart card interface
cannot detect framing errors.
Bit 4: ERS
Description
0
Receiving ended normally with no error signal.
(Initial value)
ERS is cleared to 0 when the chip is reset or enters standby mode, or when
software reads ERS after it has been set to 1, then writes 0 in ERS.
1
An error signal indicating a parity error was transmitted from the receiving side.
ERS is set to 1 if the error signal sampled is low.
Note: The ERS flag maintains its state even when the TE bit in SCSCR is cleared to 0.
Rev. 5.00 Dec 12, 2005 page 547 of 1034
REJ09B0254-0500