SH7727 Datasheet, PDF (936/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 28 A/D Converter
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the MULTI bit select the
analog input channels. Clear the ADST bit to 0 before changing the channel selection.
Channel Selection
CH2
CH1
0
0
1
1
0
1
CH0
0
1
0
1
0
1
0
1
Description
Single Mode
(MULTI = 0)
reserved
reserved
AN2
AN3
AN4
AN5
AN6
AN7
Multi Mode
(MULTI = 1)
reserved
reserved
AN2
AN2, AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
28.2.3 A/D Control Register (ADCR)
Bit: 7
6
5
4
3
2
1
0
TRGE1 TRGE0 SCN RESVD1 RESVD2 —
—
—
Initial value: 0
0
0
0
0
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R
R
R
ADCR is an 8-bit read/write register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'07 by a reset and in standby mode.
Bits 7 and 6—Trigger Enable (TRGE1, TRGE0): Enables or disables external triggering of
A/D conversion.
Bit 7: TRGE1
0
0
1
1
Bit 6: TRGE0
0
1
0
1
Description
When an external trigger is input, the A/D conversion does not
start
(Initial value)
The A/D conversion starts at the falling edge of an input signal
from the external trigger pin (ADTRG).
Rev. 5.00 Dec 12, 2005 page 864 of 1034
REJ09B0254-0500