SH7727 Datasheet, PDF (467/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bits 11 to 8 — DMA Channel 2 Request Assign 3 to 0 (CH2RID3 to CH2RID0): These bits
select DMA requests from DMA channel 2.
Bits 11 to 8:
CH2RID3 to CH2RID0
0000
0001
0010
1001
1010
Description
Unused
(Initial value)
USBF (USB function) reception requests to the DMA are selected from
channel 2
USBF (USB function) transmission requests to the DMA are selected
from channel 2
SIOF reception requests to the DMA are selected from channel 2
SIOF transmission requests to the DMA are selected from channel 2
Bits 7 to 4— DMA Channel 1 Request Assign 3 to 0 (CH1RID3 to CH1RID0): These bits
select DMA requests from DMA channel 1.
Bits 7 to 4:
CH1RID3 to CH1RID0
0000
0001
0010
1001
1010
Description
Unused
(Initial value)
USBF (USB function) reception requests to the DMA are selected from
channel 1
USBF (USB function) transmission requests to the DMA are selected
from channel 1
SIOF reception requests to the DMA are selected from channel 1
SIOF transmission requests to the DMA are selected from channel 1
Bits 3 to 0— DMA Channel 0 Request Assign 3 to 0 (CH0RID3 to CH0RID0): These bits
select DMA requests from DMA channel 0.
Bits 3 to 0:
CH0RID3 to CH0RID0
0000
0001
0010
1001
1010
Description
Unused
(Initial value)
USBF (USB function) reception requests to the DMA are selected from
channel 0
USBF (USB function) transmission requests to the DMA are selected
from channel 0
SIOF reception requests to the DMA are selected from channel 0
SIOF transmission requests to the DMA are selected from channel 0
Rev. 5.00 Dec 12, 2005 page 395 of 1034
REJ09B0254-0500