SH7727 Datasheet, PDF (206/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 4 Exception Handling
Exception Current
Type
Instruction Exception Event
Exception Vector
Priority^*1 Order
Address
Vector Offset
General
Completed Nonmaskable interrupt 3
—
—
interrupt
requests
External hardware
4^*3
—
—
interrupt
H-UDI interrupt
4^*3
—
—
H'00000600
H'00000600
H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest.
2. The user defines the break point traps. 1 is a break point before instruction execution
and 11 is a break point after instruction execution. For an operand break point, use 11.
3. Use software to specify relative priorities of external hardware interrupts and peripheral
module interrupts (see section 7, Interrupt Controller (INTC)).
4. See section 4.5.2, General Exceptions for details.
4.2.3 Acceptance of Exceptions
Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All
exception events are prioritized to establish an acceptance order whenever two or more exception
events occur simultaneously. When a power-on reset and a manual reset occur simultaneously, the
power-on reset has priority.
All general exception events occur in a relative order in the execution sequence of an instruction
(i.e., execution order), but are handled at priority level 2 in instruction-stream order (i.e., program
order), where an exception detected in a preceding instruction is accepted prior to an exception
detected in a subsequent instruction.
Three general exception events (general illegal instruction exception, unconditional trap exception,
and illegal slot instruction exception) are detected in the decode stage (ID stage) of different
instructions and are mutually exclusive events in the instruction pipeline. They have the same
execution priority. Figure 4.2 shows the order of general exception acceptance.
Rev. 5.00 Dec 12, 2005 page 134 of 1034
REJ09B0254-0500