SH7727 Datasheet, PDF (998/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 31 User-Debugging Interface (H-UDI)
31.4.2 Reset Configuration
Table 31.4 Reset Configuration
ASDMD0^*1
RESETP
TRST
Chip State
H
L
L
Normal reset and H-UDI reset
H
Normal reset
H
L
H-UDI reset only
H
Normal operation
L
L
L
Reset hold^*2
H
ASE user mode^*3: Normal reset
ASE break mode^*3: RESETP assertion masked
H
L
H-UDI reset only
H
Normal operation
Notes: 1. Performs main chip mode and ASE mode settings
ASEMD0 = H, main chip mode
ASEMD0 = L, ASE mode
When user system is used alone without using emulator or H-UDI, set ASEMD0 to H.
2. During ASE mode, reset hold is enabled by setting RESETP and TRST pins at low level
for a constant cycle. In this state, the CPU does not start up, even if RESETP is set to
high level. When TRST is set to high level, H-UDI operation is enabled, but the CPU
does not start up. The reset hold state is cancelled by the following:
• Boot request from H-UDI (boot sequence)
• Another RESETP assert (power-on reset)
3. There are two ASE modes, one for executing software in the emulator’s firmware (ASE
break mode) and one for executing user software (ASE user mode).
Rev. 5.00 Dec 12, 2005 page 926 of 1034
REJ09B0254-0500