SH7727 Datasheet, PDF (690/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
Bit 0—Receiving Operation Reset (RXRST): Setting to this bit becomes effective immediately.
After the setting 1 to this bit becomes effective, SIOF initializes the following registers and stop
receiving from SIORXD.
1. SIRDR register
2. Receiving FIFO write pointer and read pointer
3. RCRDY, RFFUL, and RDREQ bits of SISTR register
4. RXE bit
SIOF is cleared automatically when this bit completes the reset, so 0 is always read from this bit.
Bit 0: RXRST
0
1
Description
Receiving operation is not reset
Receiving operation is reset
(Initial value)
20.2.7 FIFO Control Register (SIFCTR)
This register set trigger point and show current available area of Transmit and Receive FIFO. This
register is initialized at power on reset or software reset.
Bit:
Initial value:
R/W:
15
TFWM2
0
R/W
14
TFWM1
0
R/W
13
TFWM0
0
R/W
12
TFUA4
1
R
11
TFUA3
0
R
10
TFUA2
0
R
9
TFUA1
0
R
8
TFUA0
0
R
Bit:
Initial value:
R/W:
7
6
RFWM2 RFWM1
0
0
R/W
R/W
5
RFWM0
0
R/W
4
RFUA4
0
R
3
RFUA3
0
R
2
RFUA2
0
R
1
RFUA1
0
R
0
RFUA0
0
R
Rev. 5.00 Dec 12, 2005 page 618 of 1034
REJ09B0254-0500