SH7727 Datasheet, PDF (410/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Tr
CKIO,
CKIO2
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS3
CAS
RD/WR
DQMxx
Tc1
Td1
Tpc
D31 to D0
BS
Figure 12.15 Basic Timing for Synchronous DRAM Single Read
Burst Write: The timing chart for a burst write is shown in figure 12.16. In this LSI, a burst write
occurs only in the event of cache write-back. In a burst write operation, following the Tr cycle in
which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3
cycles, and a WRITA command that performs auto-precharge is issued in the Tc4 cycle. In the
write cycle, the write data is output at the same time as the write command. In case of the write
with auto-precharge command, precharging of the relevant bank is performed in the synchronous
DRAM after completion of the write command, and therefore no command can be issued for the
same bank until precharging is completed. Consequently, in addition to the precharge wait cycle,
Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started
following the write command. Issuance of a new command for the same bank is postponed during
this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR.
Rev. 5.00 Dec 12, 2005 page 338 of 1034
REJ09B0254-0500