SH7727 Datasheet, PDF (509/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Peripheral clock
(Pφ)
CMCNT0
input clock
CMCNT0
CMCOR0
Compare
match signal
CMF
Section 14 Direct Memory Access Controller (DMAC)
N
0
N
CMI
Figure 14.29 Timing of CMF Setting
Compare-Match Flag Clear Timing
The CMF bit in the CMCSR0 register is cleared by writing 0 to the bit after reading 1. Figure
14.30 shows the timing when the CMF bit is cleared by the CPU.
Peripheral clock
(Pφ)
CMF
CMCSR0 write cycle
T₁
T₂
Figure 14.30 Timing of CMF Clear by the CPU
Rev. 5.00 Dec 12, 2005 page 437 of 1034
REJ09B0254-0500