SH7727 Datasheet, PDF (312/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
Bit 5— Module Stop 15 (MSTP15): Specifies halting the clock supply to the AFE interface
(AFE IF). When the MSTP15 bit is set to 1, the clock supply to the AFE interface is halted.
Bit 5: MSTP15
0
1
Description
AFE interface runs
Clock supply to AFE interface halted
(Initial value)
Bit 4— Module Stop 14 (MSTP14): Specifies halting the clock supply to the USB function
module (USBF). When the MSTP14 bit is set to 1, the clock supply to the USBF is halted.
Bit 4: MSTP14
0
1
Description
USBF runs
Clock supply to USBF halted
(Initial value)
Bit 3—Module Stop 13 (MSTP13): Specifies halting the clock supply to the USB host controller
(USBH). When the MSTP13 bit is set to 1, the clock supply to the USBH is halted.
Bit 3: MSTP13
Description
0
USBH runs
1
Clock supply to USBH halted
Note: This bit should not be set to 1 when MSTP14 (bit 4) is 0.
(Initial value)
Bit 2——Reserved: This bit is always read as 0. The write value should always as 0.
Bit 1— Module Stop 11 (MSTP11): Specifies halting the clock supply LCD Controller (LCDC).
When the MSTP11 bit is set to 1, the clock supply to the LCDC is halted.
Bit 1: MSTP11
0
1
Description
LCDC runs
Clock supply to LCDC halted
(Initial value)
Bit 0— Module Stop 10 (MSTP10): Specifies halting the clock supply to PC Card Controller
(PCC). When the MSTP10 bit is set to 1, the clock supply to the PCC is halted.
Bit 0: MSTP10
0
1
Description
PCC runs
Clock supply to PCC halted
(Initial value)
Rev. 5.00 Dec 12, 2005 page 240 of 1034
REJ09B0254-0500