SH7727 Datasheet, PDF (856/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
25.2.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR)
LDACLNR specifies the timing to toggle the AC modulation signal (LCD current-alternating
signal) of the LCD module.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
— ACLN4 ACLN3 ACLN2 ACLN1 ACLN0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W
Bits 15 to 5—Reserved
Bits 4 to 0—AC Line Number (ACLN): Set the line number where the LCD current-alternating
signal of the LCD module is toggled (unit: line).
Subtract 1 from the setting (0 to 31 (H'1F)).
Note: When the total line number of the LCD panel is even, set an even number so that toggling
is performed at an odd line.
Example: For toggling every 13 lines
ACLN = 13 – 1 = 12 = H'0C
25.2.16 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to start the Vsync interrupt (LCDCI).
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
— VINT —
—
— VINTE —
—
—
—
—
—
— VINTS
SEL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R
R
R
R/W
R
R
R
R
R
R
R R/W
Bits 15 to 13, 11 to 9, and 7 to 1—Reserved
Rev. 5.00 Dec 12, 2005 page 784 of 1034
REJ09B0254-0500