SH7727 Datasheet, PDF (600/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Figure 17.16 shows an example of SCI receive operation using a multiprocessor format.
Start Data
1 _bit (ID1)
Serial
data
0 D₀ D₁
MPIE
Stop Start Data
MPB bit bit (data 1)
D₇ 1 1 0 D₀ D₁
Stop
MPB bit
1
D₇
0
1 ^Idling
(marking)
RDRF
RDR
value
ID1
RXI interrupt request Reads RDR data with
(multiprocessor interrupt) the RXI interrupt
generated, MPIE = 0
processing routine
and clears RDRF bit to 0
ID is not station’s No RXI interrupt,
ID, so MPIE bit is generated
set to 1 again
RDR state
is maintained
(a) Own ID does not match data
Serial
data
Start Data
1 _bit (ID2)
0 D₀ D₁
Stop Start Data
MPB bit bit (Data 2)
D₇ 1 1 0 D₀ D₁
Stop
MPB bit
1
D₇
0
1 ^Idling
(marking)
MPIE
RDRF
RDR
value
ID1
ID2
Data2
RXI interrupt
request
(multiprocessor
interrupt) generated,
MPIE = 0
Reads RDR data with
the RXI interrupt
processing routine
and clears
RDRF bit to 0
ID is that of station,
so reception
continues unchanged
and data is received
by the RXI interrupt
processing routine
MPIE bit
set to 1
again
(b) Own ID matches data
Figure 17.16 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 5.00 Dec 12, 2005 page 528 of 1034
REJ09B0254-0500