SH7727 Datasheet, PDF (374/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted
into physical space area 2.
• For Ordinary memory
Bit 4: A2W0
0
1
Bit 3: A2W0
0
1
0
1
Description
Inserted Wait States
WAIT Pin
0
Ignored
1
Enable
2
Enable
3
Enable
(Initial value)
• For Synchronous SDRAM
Bit 4: A2W1
0
1
Bit 3: A2W0
0
1
0
1
Description
Synchronous DRAM: CAS Latency
1
1
2
3
(Initial value)
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): Specify the number of wait states
inserted into physical space area 0. Also specify the burst pitch for burst transfer.
Bit 2:
A0W2
0
1
Bit 1:
A0W1
0
1
0
1
Bit 0:
A0W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enable
1
Enable
2
Enable
2
Enable
3
Enable
3
Enable
4
Enable
4
Enable
4
Enable
6
Enable
6
Enable
8
Enable
8
Enable
10
Enable
10
(Initial value)
Enable
Rev. 5.00 Dec 12, 2005 page 302 of 1034
REJ09B0254-0500