SH7727 Datasheet, PDF (246/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt Source
NMI
H-UDI
IRQ
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
PINT PINT0–7
PINT8–15
DMAC DEI0
DEI1
DEI2
DEI3
SCIF ERI2
RXI2
BRI2
TXI2
ADC
ADI
LCDC LCDCI
SIOF SIFERI
SIFTXI
SIFRXI
SIFCCI
USBH USBHI
USBF USBFI0
USBFI1
AFEIF AFEIFI
INTEVT Code
(INTEVT2 Code)
H'1C0 (H'1C0)
H'5E0 (H'5E0)
H'200–3C0* (H'600)
H'200–3C0* (H'620)
H'200–3C0* (H'640)
H'200–3C0* (H'660)
H'200–3C0* (H'680)
H'200–3C0* (H'6A0)
H'200–3C0* (H'700)
H'200–3C0* (H'720)
H'200–3C0* (H'800)
H'200–3C0* (H'820)
H'200–3C0* (H'840)
H'200–3C0* (H'860)
H'200–3C0* (H'900)
H'200–3C0* (H'920)
H'200–3C0* (H'940)
H'200–3C0* (H'960)
H'200–3C0* (H'980)
H'200–3C0* (H'9A0)
H'200–3C0* (H'B00)
H'200–3C0* (H'B20)
H'200–3C0* (H'B40)
H'200–3C0* (H'B60)
H'200–3C0* (H'A00)
H'200–3C0* (H'A20)
H'200–3C0* (H'A40)
H'200–3C0* (H'A 60)
Interrupt
Priority
(Initial Value)
16
15
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
IPR (Bit
Numbers)
—
—
IPRC (3–0)
IPRC (7–4)
IPRC (11–8)
IPRC (15–12)
IPRD (3–0)
IPRD (7–4)
IPRD (15–12)
IPRD (11–8)
IPRE (15–12)
IPRE (7–4)
IPRE (3–0)
IPRF(11–8)
IPRF(3–0)
IPRG(15–12)
IPRG(11–8)
IPRG(7–4)
IPRG(3–0)
Priority
within IPR
Setting Default
Unit
Priority
—
High
—
—
—
—
—
—
—
—
—
High
Low
High
Low
—
—
High
Low
—
High
Low
—
Low
Rev. 5.00 Dec 12, 2005 page 174 of 1034
REJ09B0254-0500