SH7727 Datasheet, PDF (466/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.2.5 DMA Channel Request Assign Register (CHRAR )
The DMA channel request assign register (CHRAR) is a 16-bit read/write registers that assign
requests from USBF or SIOF to each DMA channel, to each expanded DMA. It is initialized to 0
at power-on reset, or in hardware standby mode or software standby mode. These register values
are initialized to 0s after a power-on reset. The previous value is held in standby mode.
Bit:
Initial value:
R/W:
15,14,13,12
CH3RID3 to CH0RID0
0
R/W
11,10,9,8
CH2RID3 to CH2RID0
0
R/W
Bit:
Initial value:
R/W:
7,6,5,4
CH1RID3 to CH1RID0
0
R/W
3,2,1,0
CH0RID3 to CH0RID0
0
R/W
Bits 15 to 12 —DMA Channel 3 Request Assign 3 to 0 (CH3RID3 to CH3RID0): These bits
select DMA requests from DMA channel 3.
Bits 15 to 12:
CH3RID3 to CH3RID0
0000
0001
0010
1001
1010
Description
Unused
(Initial value)
USBF (USB function) reception requests to the DMA are selected from
channel 3
USBF (USB function) transmission requests to the DMA are selected
from channel 3
SIOF reception requests to the DMA are selected from channel 3
SIOF transmission requests to the DMA are selected from channel 3
Rev. 5.00 Dec 12, 2005 page 394 of 1034
REJ09B0254-0500