SH7727 Datasheet, PDF (283/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.2.6 Break Data Register B (BDRB)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB BDB
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BDRB is a 32-bit read/write register. The control bits XYE and XYS in BBRB select a data bus
for break condition B. If the XYE is 0, then BDRB specifies the break data on LDB or IDB. If the
XYE is 1, then BDB 31 to 16 specifies the break data on XDB (bits 15 to 0) and BDB 15 to 0
specifies the break data on YDB (bits 15 to 0). However, you have to choose one of two data
buses for the break. A power-on reset initializes BDRB to H'00000000.
XYE = 0
XYE = 1
BDB31 to 16
L(I) DB31 to 16
XDB15 to 0 (XYS = 0)
BDB15 to 0
L(I) DB15 to 0
YDB15 to 0 (XYS = 1)
Rev. 5.00 Dec 12, 2005 page 211 of 1034
REJ09B0254-0500