SH7727 Datasheet, PDF (141/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Data Transfer Instructions
Table 2.20 Data Transfer Instructions
Instruction
MOV #imm,Rn
MOV.W @(disp,PC),Rn
MOV.L @(disp,PC),Rn
MOV Rm,Rn
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L
MOV.B
MOV.W
MOV.L
@Rm,Rn
Rm,@–Rn
Rm,@–Rn
Rm,@–Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn)
MOV.W R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.B @(disp,Rm),R0
MOV.W @(disp,Rm),R0
MOV.L @(disp,Rm),Rn
MOV.B Rm,@(R0,Rn)
Operation
Code
imm → Sign extension
→ Rn
1110nnnniiiiiiii
(disp × 2 + PC) → Sign
extension → Rn
1001nnnndddddddd
(disp × 4 + PC) → Rn
1101nnnndddddddd
Rm → Rn
0110nnnnmmmm0011
Rm → (Rn)
0010nnnnmmmm0000
Rm → (Rn)
0010nnnnmmmm0001
Rm → (Rn)
0010nnnnmmmm0010
(Rm) → Sign extension
→ Rn
0110nnnnmmmm0000
(Rm) → Sign extension
→ Rn
0110nnnnmmmm0001
(Rm) → Rn
0110nnnnmmmm0010
Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100
Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101
Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110
(Rm) → Sign extension
→ Rn, Rm + 1 → Rm
0110nnnnmmmm0100
(Rm) → Sign extension
→ Rn, Rm + 2 → Rm
0110nnnnmmmm0101
(Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110
R0 → (disp + Rn)
10000000nnnndddd
R0 → (disp × 2 + Rn)
10000001nnnndddd
Rm → (disp × 4 + Rn)
0001nnnnmmmmdddd
(disp + Rm) → Sign
extension → R0
10000100mmmmdddd
(disp × 2 + Rm) → Sign
extension → R0
10000101mmmmdddd
(disp × 4 + Rm) → Rn
0101nnnnmmmmdddd
Rm → (R0 + Rn)
0000nnnnmmmm0100
Privileged
Mode
Cycles T Bit
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
Rev. 5.00 Dec 12, 2005 page 69 of 1034
REJ09B0254-0500